Typical TTL circuits incorporating a pulldown transistor element for sinking current from an output node include TTL buffers, TTL output gates or devices, TTL to ECL and ECL to TTL translators, etc. A prior art TTL output device or output circuit 10 is illustrated in FIG. 1. The circuit is characterized by a pulldown transistor element Q5 which sinks current from an output node V.sub.o to ground or low potential. The circuit may also include a pullup element Z which is controlled for sourcing current from the high potential TTL power supply V.sub.cc through a resistance or impedance to the output node V.sub.o.
With respect to the pullup element Z, three configurations of TTL output circuits may generally be identified. First, in the case of an active transistor pullup element such as a Darlington transistor pair, the pullup and pulldown transistor elements form a totem pole output which may be controlled with or without a phase splitter. Second, in the illustrated example of FIG. 1 the pullup element is a passive pullup element for example such as a resistance or reactance. Third, the circuit may be fabricated with an open collector at the pullup location and the user provides the pullup element, for example a passive pullup element Z from related circuitry.
The base drive transistor Q4 controls the conducting state of the pulldown transistor element Q5 and the sourcing of current through the pullup element Z. The pulldown transistor Q5 and pullup element Z are generally in opposite conducting states. In the case of an active totem pole configuration of active pullup and pulldown transistor elements at the output the base drive transistor Q4 may be configured as a phase splitter transistor. In the example of FIG. 1 the base drive transistor Q4 is an emitter follower transistor controlling the conducting state of the pulldown transistor Q5. As shown in FIG. 1, when Q5 is on there is current flow through Z into Q5 to ground.
The base of transistor Q4 is coupled to the input V.sub.IN through diode D1 at the input base node A. The diode connected transistors Q1, Q2 and Q3 coupled in series form a clamping network between the input base node A and low potential to hold the base of transistor Q4 at a voltage level sufficiently high to turn on Q4 when a high level potential signal appears at the input V.sub.IN. When a logic high level signal appears at the input node V.sub.IN, the TTL power supply V.sub.cc or high potential delivers base drive current through resistor R1 to transistor Q4. When base drive transistor Q4 is conducting, sourcing current is diverted from the pullup element Z through the collector to emitter path of emitter follower base drive transistor Q4 turning on the pulldown transistor element Q5 with base drive current through resistor R2. The pulldown transistor element Q5 sinks current from the output node V.sub.o so that the output is at logic low level potential.
When a logic low level signal appears at the input node V.sub.IN transistor Q4 is deprived of base drive current and turns off. The pulldown transistor Q5 turns off and the pullup element Z sources current to the output V.sub.o so that the output is at the logic high level potential. The illustrated TTL output circuit of FIG. 1 is therefore inverting.
During transition from low to high level potential at the input V.sub.IN, the voltage V.sub.A at input base Node A rises at a rate depending on the resistance value of R1 and the capacitance associated with junctions at Node A as illustrated by way of example in FIGS. 2A and 2B. The delay in the rise of voltage V.sub.A at Node A combined with delays associated with the capacitance of the output node V.sub.o and output load result in a total time delay TD in the transition from high to low potential at the output V.sub.o as shown in FIG. 2C. In order to increase the speed of the high to low transition at the output the resistance of R1 must be decreased in value with the accompanying disadvantage of larger steady state power consumption.